Replacing small (e.g., less than 4096 bit) traditional static random access memories (SRAM) with latch-based random access memories (LBRAM) may, in certain circumstances, relax restrictions on the layout of circuitry on an integrated circuit (chip). LBRAM is typically implemented with logic gates and does not have sense amplifiers, pre-charge circuitry, and other circuitry traditionally found in an SRAM. Advantageously, LBRAM designs can be based on the same logic architecture as on the rest of the chip, resulting in the memory circuitry having the same “pitch” or layout spacing as in the other logic circuitry. This allows for the routing of data signals through the LBRAM design (by exploiting routing “channels” or spaces within the memory layout) with the same flexibility as routing the signals through the logic circuitry, unlike SRAM designs which have more restrictions on the placing and routing of signals though the SRAM layout. Hence, LBRAMs are implemented in application specific integrated circuits (ASIC) and other complex chips at relatively low cost compared to SRAM designs. Moreover, LBRAM designs may be at least as fast, if not faster, than SRAM designs.
Latch-based memories are generally arranged to have an M word by N bits per word configuration. While the N bits at a time are typically read at a time (i.e., in parallel) from the LBRAM, it may be desirable to write less than N bits at a time into the LBRAM. Some LBRAM designs allow for less than all of the N bits to be written in a selected word without disturbing the remaining bits in the selected word. However, these designs have been found to be problematic, especially as the number of words (M) in the LBRAMs get larger (e.g., M >=1024). Such designs typically use-N write data lines to transmit data to be written to the M memory cells coupled to each of the write data lines. When data is to be written into certain memory cells, data is asserted on the corresponding write data lines by placing those data lines in a low impedance state having logic values representing the desired data value (e.g., a “zero” or a “one”). Conversely, when data is not to be written into certain memory cells, no data is asserted on the corresponding write address lines and the lines are left in a high-impedance state. Then, the N memory cells of a selected word are enabled (in a typical memory cell, a switch in the memory cell couples a bistable latch in the cell to the corresponding write data line when the cell is enabled), and the enabled memory cells coupled to the low impedance write data lines are “forced” to store the data value on the corresponding write data line (i.e., the memory cells are overwritten with the data value on the corresponding write data line). In theory, enabled memory cells coupled to the high impedance write data lines will retain the data stored therein. However, because the write data lines may have significant capacitive loading, when the enabled memory cell is coupled to the high-impedance write data line, the data stored in the cell may unintentionally change state.